Jun 06, 2017 02:01 PM EDT
The trio made up of IBM, Globalfoundries, and Samsung replaced the common fin field effect transistor (FinFET) design. It instead shifted to stacks of silicon nanosheets using extreme ultraviolet lithography to create the breakthrough 7nm chip. The transistor manufacturing process that the three developed will pave the way for 5-nanometer chips which can fit 30 billion transistors into a very small space.
The 5-nanometer chips are about the size of a fingernail, Engadget reported. It is an improvement from the 20 billion transistors that fitted into a 7-nm chip a few years ago. With the technique, IBM says it will help the company with its cognitive computing efforts and the Internet of Things and other tasks that are data sensitive.
Also expected to be impacted by the 5-nanometer chips are mobile devices as smartphones will have two to three times more juice than current gadgets. However, the tech website reminds that real-world example of devices using the tiny chip is not expected yet, at least until 2018 at the earliest.
NDTV reported that IBM will present the process details for the 5-nanometer chips at the 2017 Symposia on VLSI Technology and Circuits Conference which will be held in Japan. The company estimates the new chip will provide 40 percent performance enhancement at a fixed power. It could translate into 75 percent power savings at matched performance for future gadgets in favor of demands of mobile devices, virtual reality, and artificial intelligence systems.
Dan Hutcheson, the CEO of VLSI Research, explains that FinFET is running out of steam. It is sufficient only for 7-nm chips. At 5-nanometers, to keep the scaling and transistor working, there was a need to move to a different structure. The three companies went horizontal, instead of using the vertical fin structure of FinFET, layered silicon nanosheets in a way that resulted effectively in a fourth gate. It is like the FinFET being turned sideways and stacked on top of each other.
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